FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: Reluctant to pursue it as we are not using Petalinux:. Cadence GEM rev 0x at 0xec irq Anyone else had it work? However, eth1 still doesn’t work correctly. Haven’t worked on this in a couple of years. There was a little communication confusion with Xilinx.

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I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 marrvell – other addresses do not respond.

Linuc verified that both PHYs respond when using the u-boot mdio commands, however, when running the Linux kernel code, it appears to ignore or not see the addresses in the device tree, and it also seems to not identify PHY1 correctly, attaching a “Generic PHY” driver to it. Auto-suggest helps you quickly narrow down your search results by suggesting possible matches as you type.

However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth Have you tried with slightly rearranged device tree like this?


Check the reset pin to the PHYs.

net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]

Reluctant to pursue it as we are not using Petalinux:. Thu Linkx 18 Build the device tree blob, and copy uImage and the.

We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot. I had seen that, but we run both PHYs a 1. I’ll update you when I have more information. However, eth1 still doesn’t work correctly.

Linux source code: drivers/net/phy/marvell.c (v) – Bootlin

It’s not being released in the petalinux Note that I am using two different sub-nets – the Not sure about the dsa or link. Hoping to get a pre-release of the We have a custom board with a Zynq using two Marvell 88e PHYs for dual ethernet lnux have not been able to get eth1 up and running on xilinx-linux eth0 works fine. I’ve tried your device tree example as well as different examples found:.

So I would suggest you to try testing the setup in If they both operate at 2.


Please upgrade to a Xilinx. ChromeFirefoxInternet Explorer 11Safari. Cadence GEM rev 0x at 0xeb irq Hope this helps everyone with this problem What other kernel settings did you have to enable to allow the Marvell 88e PHY to have the correct phu from petalinux?

Thanks for the advice. I suspect this is a software issue. FYI, Tool and Software tags: We are not able to run our dual GEM config.

Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums

I will post when I get the new release and test it. It’s likely that a hardware workaround in the fabric is easier to implement than digging into the Linux core software. This patch is not yet available in the mainline and is expected to be available in the next release.

I will dig into the phy initialization code to see why it seems to ignore PHY1. If they both operate at 3.